// s1 values (9 bits)
// ExtCacheWrite_s1, ExtCacheRead_s1, ExtCacheReset_s1,
// WriteDone_s1, CacheAddr_s1 (4 bits), WriteMem_s1

// s2 values (22 bits)
// BusGrant_s2, CacheDataToChip_s2 (4 bits), CacheDataFromChip_s2 (4 bit),
// WriteStall_s2, ReadStall_s2, ReadMatch_s2, BusRelease_s2, 
// BusRequest_s2, SysBusAddr (4 bits), SysBusData (4 bits)

// 0
// s1 reset
0010xxxxxxxxxxxxxxxxxx

// 1
// s2 reset
0xxxxxxxx00000xxxxxxxx

// 2
// s1 cache write 1 (addr: 0001)
100000010xxxxxxxxxxxxx

// 3
// s2 cache write 1 (data: 1000)
01000xxxx10000xxxxxxxx

// 4
// s1 cache write 1 (tag update)
100000010xxxxxxxxxxxxx

// 5
// s2 cache write 1
01000xxxx00000xxxxxxxx

// 6
// s1 cache write 2 (addr: 0010)
100000100xxxxxxxxxxxxx

// 7
// s2 cache write 2 (data: 0100)
00100xxxx10000xxxxxxxx

// 8
// s1 cache write 2 (tag update)
100000100xxxxxxxxxxxxx

// 9
// s2 cache write 2
00100xxxx00000xxxxxxxx

// a
// s1 cache write 3 (addr: 0100)
100001000xxxxxxxxxxxxx

// b
// s2 cache write 3 (data: 0010)
00010xxxx10000xxxxxxxx

// c
// s1 cache write 3 (tag update)
100001000xxxxxxxxxxxxx

// d
// s2 cache write 3
00010xxxx00000xxxxxxxx

// e
// s1 cache write 4 (addr: 0010)
// note: write merge
100000100xxxxxxxxxxxxx

// f
// s2 cache write 4 (data: 1111)
01111xxxx00000xxxxxxxx

// 10
// s1 idle cycle
0000xxxx0xxxxxxxxxxxxx

// 11
// s2 idle cycle
0xxxxxxxx00000xxxxxxxx

// 12
// s1 bus read 1
0000xxxx0xxxxxxxxxxxxx

// 13
// s2 bus read 1 (request bus)
0xxxxxxxx00001xxxxxxxx

// 14
// s1 bus read 1 (invalidate)
0000xxxx0xxxxxxxxxxxxx

// 15
// s2 bus read 1 (bus granted)
1xxxxxxxx00000xxxxxxxx

// 16
// s1 bus read 1 (write to bus), cache write 5 (addr: 1111)
100011111xxxxxxxxxxxxx

// 17
// s2 bus read 1 (write to bus), cache write 5 (data: 1100)
01100xxxx1000000011000

// 18
// s1 bus read 1 (done), cache write 5 (update tag)
1001111100000000000000

// 19
// s2 bus read 1 (done), cache write 5
01100xxxx00010xxxxxxxx

// 1a
// s1 cache write 6 (addr: 1010)
100010100xxxxxxxxxxxxx

// 1b
// s2 cache write 6 (data: 0000)
00000xxxx10000xxxxxxxx

// 1c
// s1 cache write 6 (tag update)
100010100xxxxxxxxxxxxx

// 1d
// s2 cache write 6
00000xxxx00000xxxxxxxx

// 1e
// s1 cache write 7 (addr: 0111)
// note: queue full
100001110xxxxxxxxxxxxx

// 1f
// s2 cache write 7 (data: 1110)
01110xxxx10000xxxxxxxx

// 20
// s1 bus read 2
100001110xxxxxxxxxxxxx

// 21
// s2 bus read 2 (request bus)
01110xxxx10001xxxxxxxx

// 22
// s1 bus read 2 (invalidate)
100001110xxxxxxxxxxxxx

// 23
// s2 bus read 2 (waiting for bus grant)
01110xxxx10001xxxxxxxx

// 24
// s1 bus read 2, cache write 7
100001110xxxxxxxxxxxxx

// 25
// s2 bus read 2 (bus grant), cache write 7
11110xxxx1000000101111

// 26
// s1 bus read 2 (write to bus), cache write 7 (update tag)
100001111xxxxxxxxxxxxx

// 27
// s2 bus read 2 (write to bus), cache write 7
01110xxxx0000000101111

// 28
// s1 cache read 1 (addr: 1111), bus read 2
010011111xxxxxxxxxxxxx

// 29
// s2 cache read 1 (data: 1100), bus read 2
0xxxx11000010000101111

// 2a
// s1 bus read 2 (write done), cache idle
0001xxxx0xxxxxxxxxxxxx

// 2b
// s2 bus read 2 (done), cache idle
0xxxxxxxx00010xxxxxxxx

// 2c
// s1 cache write 8 (addr: 1010)
// note: write merge
100010100xxxxxxxxxxxxx

// 2d
// s2 cache write 8 (data: 1010)
01010xxxx00000xxxxxxxx

// 2e
// s1 cache read 2 (addr: 0000)
010000000xxxxxxxxxxxxx

// 2f
// s2 cache read 2
0xxxxxxxx00000xxxxxxxx

// 30
// s1 bus read 3, cache read 3 (addr: 0100)
010001000xxxxxxxxxxxxx

// 31
// s2 bus read 3 (request bus), cache read 3
0xxxx001000101xxxxxxxx

// 32
// s1 bus read 3 (invalidate), cache read 4 (addr: 1111)
010011110xxxxxxxxxxxxx

// 33
// s2 bus read 3, cache read 4
0xxxxxxxx01101xxxxxxxx

// 34
// s1 bus read 3 (wait for bus), cache read 4
010011110xxxxxxxxxxxxx

// 35
// s2 bus read 3, cache read 4 (data: 1100)
0xxxx110000101xxxxxxxx

// 36
// s1 bus read 3 (waiting for bus), cache write 9 (addr: 0000)
100000000xxxxxxxxxxxxx

// 37
// s2 bus read 3 (waiting for bus), cache write 9 (data: 1001)
01001xxxx10001xxxxxxxx

// 38
// s1 bus read 3 (waiting for bus), cache write 9 (tag update)
100000000xxxxxxxxxxxxx

// 39
// s2 bus read 3 (waiting for bus), cache write 9
01001xxxxxxxx1xxxxxxxx

// 3a
// s1 bus read 3 (waiting for bus), cache write 10 (addr: 1111)
// note: write merge
100011110xxxxxxxxxxxxx

// 3b
// s2 bus read 3 (waiting for bus), cache write 10 (data: 1111)
01111xxxx00001xxxxxxxx

// 3c
// s1 bus read 3 (waiting for bus), cache write 11 (addr: 0101)
// note: buffer full
100001010xxxxxxxxxxxxx

// 3d
// s2 bus read 3 (bus granted), cache write 11 (data: 0011)
10011xxxx1000001000010

// 3e
// s1 bus read 3 (write to bus), cache write 11 (addr: 0101)
100001011xxxxxxxxxxxxx

// 40
// s2 bus read 3 (write to bus), cache write 11 (data: 0011)
00011xxxx1000001000010

// 41
// s1 bus read 3 (done), cache write 11 (addr: 0101)
// note: buffer full
100101010xxxxxxxxxxxxx

// 42
// s2 bus read 3 (done), cache write 11 (addr: 0011)
00011xxxx10010xxxxxxxx

// 43
// cache write 11 (addr: 0101)
100001010xxxxxxxxxxxxx

// 44
// cache write 11 (addr: 0011)
00011xxxx10000xxxxxxxx

// 45
// s1 bus read 4, cache write 11 (addr: 0101)
100001010xxxxxxxxxxxxx

// 46
// s2 bus read 4 (request bus), cache write 11 (data: 0011)
00011xxxx10001xxxxxxxx

// 47
// s1 bus read 4 (invalidate), cache write 11 (addr: 0101)
100001010xxxxxxxxxxxxx

// 48
// s2 bus read 4 (bus granted), cache write 11 (data: 0011)
10011xxxx1000011111111

// 49
// s1 bus read 4 (write to bus), cache write 11 (addr: 0101)
100001011xxxxxxxxxxxxx

// 4a
// s2 bus read 4 (write to bus), cache write 11 (data: 0011)
00011xxxx1000011111111

// 4b
// s1 bus read 4 (write done), cache write 11 (tag update)
100101010xxxxxxxxxxxxx

// 4c
// s2 bus read 4 (write done), cache write 11
00011xxxx00010xxxxxxxx

// 4d
// s1 cache idle
0000xxxx0xxxxxxxxxxxxx

// 4e
// s2 cache idle
0xxxxxxxx00000xxxxxxxx

// 4f
// s1 bus read 5, cache read 5 (addr: 1010)
010010100xxxxxxxxxxxxx

// 50
// s2 bus read 5 (request bus), cache read 5 (data: 1010)
0xxxx101000101xxxxxxxx

// 51
// s1 bus read 5 (invalidate), cache read 6 (addr: 1010)
010010100xxxxxxxxxxxxx

// 52
// s2 bus read 5 (wait for bus grant), cache read 6
0xxxxxxxx01001xxxxxxxx

// 53
// s1 bus read 5 (wait for bus grant), cache read 6 (addr: 1010)
010010100xxxxxxxxxxxxx

// 54
// s2 bus read (bus granted), cache read 6 (no mtach)
10000xxxx0000010101010

// 55
// s1 bus read 5 (write to bus)
0000xxxx1xxxxxxxxxxxxx

// 56
// s2 bus read 5 (write to bus)
0xxxxxxxx0000010101010

// 57
// s1 bus read 5 (done)
0001xxxx0xxxxxxxxxxxxx

// 58
// s2 bus read 5 (done)
0xxxxxxxx00010xxxxxxxx

// 59
// s1 idle
0000xxxx0xxxxxxxxxxxxx

// 5a
// s2 idle
0xxxxxxxx00000xxxxxxxx

// 5b
// s1 bus read 6
0000xxxx0xxxxxxxxxxxxx

// 5c
// s2 bus read 6 (request bus)
0xxxxxxxx00001xxxxxxxx

// 5d
// s1 bus read 6 (invalidate)
0000xxxx0xxxxxxxxxxxxx

// 5e
// s2 bus read 6 (bus granted)
1xxxxxxxx0000001111110

// 5f
// s1 bus read 6 (write to bus)
0000xxxx1xxxxxxxxxxxxx

// 60
// s2 bus read 6 (write to bus)
0xxxxxxxx0000001111110

// 61
// s1 bus read 6 (done)
0001xxxx0xxxxxxxxxxxxx

// 62
// s2 bus read 6 (done)
0xxxxxxxx00010xxxxxxxx

// 63
// s1 idle
0000xxxx0xxxxxxxxxxxxx

// 64
// s2 idle
0xxxxxxxx00000xxxxxxxx

// 65
// s1 bus read 7
0000xxxx0xxxxxxxxxxxxx

// 66
// s2 bus read 7 (request bus)
0xxxxxxxx00001xxxxxxxx

// 67
// s1 bus read 7 (invalidate)
0000xxxx0xxxxxxxxxxxxx

// 68
// s2 bus read 7 (bus granted)
1xxxxxxxx0000000001001

// 69
// s1 bus read 7 (write to bus)
0000xxxx1xxxxxxxxxxxxx

// 6a
// s2 bus read 7 (write to bus)
0xxxxxxxx0000000001001

// 6b
// s1 bus read 7 (done)
0001xxxx0xxxxxxxxxxxxx

// 6c
// s2 bus read 7 (done)
0xxxxxxxx00010xxxxxxxx

// 6d
// s1 idle
0000xxxx0xxxxxxxxxxxxx

// 6e
// s2 idle
0xxxxxxxx00000xxxxxxxx

// 6f
// s1 bus read 8
0000xxxx0xxxxxxxxxxxxx

// 70
// s2 bus read 8 (request bus)
0xxxxxxxx00001xxxxxxxx

// 71
// s1 bus read 8 (invalidate)
0000xxxx0xxxxxxxxxxxxx

// 72
// s2 bus read 8 (bus granted)
1xxxxxxxx0000001010011

// 73
// s1 bus read 8 (write to bus)
0000xxxx1xxxxxxxxxxxxx

// 74
// s2 bus read 8 (write to bus)
0xxxxxxxx0000001010011

// 75
// s1 bus read 8 (done)
0001xxxx0xxxxxxxxxxxxx

// 76
// s2 bus read 8 (done)
0xxxxxxxx00010xxxxxxxx

// 77
// s1 idle
0000xxxx0xxxxxxxxxxxxx

// 78
// s2 idle
0xxxxxxxx00000xxxxxxxx

// 79
// s1 idle
0000xxxx0xxxxxxxxxxxxx

// 7a
// s2 idle
0xxxxxxxx00000xxxxxxxx


// new set of test vectors


// 7b
// s1 reset
0010xxxxxxxxxxxxxxxxxx

// 7c
// s2 reset
0xxxxxxxx00000xxxxxxxx

// 7d
// s1 cache read 7 (addr: 1010)
010010100xxxxxxxxxxxxx

// 7e
// s2 cache read 7 (no match)
0xxxxxxxx00000xxxxxxxx

// 80
// s1 idle
0000xxxx0xxxxxxxxxxxxx

// 81
// s2 idle
0xxxxxxxx00000xxxxxxxx

// 82
// s1 cache write 12 (addr: 0001)
100000010xxxxxxxxxxxxx

// 83
// s2 cache write 12 (data: 0001)
00001xxxx10000xxxxxxxx

// 84
// s1 cache write 12 (tag update)
100000010xxxxxxxxxxxxx

// 85
// s2 cache write 12 (done)
00001xxxx00000xxxxxxxx

// 86
// s1 idle
0000xxxx0xxxxxxxxxxxxx

// 87
// s2 idle
0xxxxxxxx00000xxxxxxxx

// 88
// s1 cache read 8 (addr: 0001), bus read 9 (addr: 0001)
010000010xxxxxxxxxxxxx

// 89
// s2 cache read 8 (data: 0001), bus read 9 (data: 0001, request bus)
0xxxx000100101xxxxxxxx

// 8a
// s1 cache read 9 (addr: 0001), bus read 9 (invalidate)
010000010xxxxxxxxxxxxx

// 8b
// s2 cache read 9 (stalled), bus read 9 (wait for bus grant)
0xxxxxxxx01001xxxxxxxx

// 8c
// s1 cache read 9 (addr: 0001), bus read 9 (wait for bus grant)
010000010xxxxxxxxxxxxx

// 8d
// s2 cache read 9 (no match), bus read 9 (bus granted)
1xxxxxxxx0000000010001

// 8e
// s1 bus read 9 (write to bus), cache write 13 (addr: 0010)
100000101xxxxxxxxxxxxx

// 8f
// s2 bus read 9 (write to bus), cache write 13 (data: 0010)
00010xxxx1000000010001

// 90
// s1 bus read 9 (write to bus), cache write 13 (tag update)
100000101xxxxxxxxxxxxx

// 91
// s2 bus read 9 (write to bus), cache write 13 (done)
00010xxxx0000000010001

// 92
// s1 bus read 9 (write done), cache write 14 (addr: 0100)
100101000xxxxxxxxxxxxx

// 93
// s2 bus read 9 (bus release), cache write 14 (data: 0100)
00100xxxx10010xxxxxxxx

// 94
// s1 cache write 14 (tag update)
100001000xxxxxxxxxxxxx

// 95
// s2 cache write 14 (done)
00100xxxx00000xxxxxxxx

// 96
// s1 cache read 10 (addr: 0010)
010000100xxxxxxxxxxxxx

// 97
// s2 cache read 10 (data: 0010)
0xxxx001000100xxxxxxxx

// 98
// s1 bus read 10 (addr: 0010), cache write 15 (addr: 0010)
100000100xxxxxxxxxxxxx

// 99
// s2 bus read 10 (data: 0010, request bus), 
// cache write 15 (data: 1111, stalled)
01111xxxx10001xxxxxxxx

// 9a
// s1 bus read 10 (invalidate), cache write 15 (stalled)
100000100xxxxxxxxxxxxx

// 9b
// s2 bus read 10 (wait for bus), cache write 15 (stalled)
01111xxxx10001xxxxxxxx

// 9c
// s1 bus read 10 (wait for bus), cache write 15 (addr: 0010)
100000100xxxxxxxxxxxxx

// 9d
// s2 bus read 10 (bus granted), cache write 15 (data: 0010)
11111xxxx1000000100010

// 9e
// s1 bus read 10 (write to bus), cache write 15 (tag update)
100000101xxxxxxxxxxxxx

// 9f
// s2 bus read 10 (write to bus), cache write 15 (done)
01111xxxx0000000100010

// a0
// s1 bus read 10 (write to bus), cache read 11 (addr: 0010)
010000101xxxxxxxxxxxxx

// a1
// s2 bus read 10 (write to bus), cache read 11 (data: 1111)
0xxxx11110010000100010

// a2
// s1 bus read 10 (write done), cache write 16 (addr: 1000)
100110000xxxxxxxxxxxxx

// a3
// s2 bus read 10 (bus release), cache write 16 (data: 1000)
01000xxxx10010xxxxxxxx

// a4
// s1 cache write 16 (tag update)
100010000xxxxxxxxxxxxx

// a5
// s2 cache write 16 (write done)
01000xxxx00000xxxxxxxx

// a6
// s1 idle
0000xxxx0xxxxxxxxxxxxx

// a7
// s2 idle
0xxxxxxxx00000xxxxxxxx