Modern microprocessors usually have special on-chip hardware devoted to queueing cache-to-from-memory operations, i.e., reads and writes due to read and write misses, in order to decrease mainly the cycle time of the cache. We have implemented such queueing hardware on a separate chip as a design exercise and here's a brief description of the specific functionality of the chip, how it's been implemented, some of the design decisions and compromises we made, and some simulation & fault coverage issues.