Simulation

• Verilog Model

Simulation of the Verilog model was done using a simple program file that sent in a vector containing the inputs and expected outputs for every clock phase. The actual output was checked against the expected value using a stimulus file that would indicate errors during the simulation.
• Layout

Simulation of the actual layout (created in Magic) was done by extracting the netlist, then converting it to an irsim file. The Verilog program file was then converted to an irsim command file, which could then be used to indicate errors during simulation.

Fault Coverage

• Fault coverage testing was done using ifsim by initially running the command file generated for simulation, and then using the "faultsim" command to randomly insert errors. Fault coverage data was based on how many of these errors the command file caught.
• With 100% seeding (894 actual faults seeded), the fault coverage was 93.62%.

linma@cs.stanford.edu