/////////////////////////////////////////////////////////////////////////////
// Block Name:  stimulus.v
// Author:      Lin Ma & Sopan Joshi
/////////////////////////////////////////////////////////////////////////////
module stimulus(phi1, phi2,
		// signals from cache to chip
		ExtCacheWrite_s1, ExtCacheRead_s1, ExtCacheReset_s1,
		CacheAddr_s1, CacheData_s2,
		// signals from chip to cache
		WriteStall_s2, ReadStall_s2, ReadMatch_s2,
		// signals from bus to chip
		BusGrant_s2, WriteDone_s1,
		// signals to bus from chip
		BusRelease_s2, WriteMem_s1, BusRequest_s2,
		SysBusAddr, SysBusData);
/////////////////////////////////////////////////////////////////////////////
  input    		phi1,           // clock phase 1
                	phi2;           // clock phase 2
  // signals from cache to chip
  output		ExtCacheWrite_s1, 
			ExtCacheRead_s1, 
			ExtCacheReset_s1;

  output	[3:0]	CacheAddr_s1;

  inout		[3:0]	CacheData_s2;

  // signals from chip to cache
  input			WriteStall_s2, 
			ReadStall_s2, 
			ReadMatch_s2;

  // signals from bus to chip
  output		BusGrant_s2, 
			WriteDone_s1;

  // signals to bus from chip
  input			BusRelease_s2, 
			WriteMem_s1, 
			BusRequest_s2;

  input		[3:0]	SysBusAddr, 
			SysBusData;
/////////////////////////////////////////////////////////////////////////////
  // storage for outputs
  reg			ExtCacheWrite_s1,
			ExtCacheRead_s1,
			ExtCacheReset_s1,
			BusGrant_s2,
			WriteDone_s1;
  reg		[3:0]	CacheAddr_s1;
  reg		[3:0]	CacheDataToChip_s2;

  // storage for inputs
  reg		[3:0]	CacheDataFromChip_s2;
  reg			WriteStallReg_s2,
			ReadStallReg_s2,
			ReadMatchReg_s2,
			BusReleaseReg_s2,
			WriteMemReg_s1,
			BusRequestReg_s2;
  reg		[3:0]	SysBusAddrReg;
  reg		[3:0]	SysBusDataReg;

  // special storage
  reg			ExtCacheWrite_s2;
/////////////////////////////////////////////////////////////////////////////
  // internal variables
  reg		[21:0]	Prog[255:0];
  reg		[7:0]	ProgCntr;
  reg		[21:0]	Temp;

`define	NOP	22'b1111111111111111111111

  // initialize and load program file
  initial
    begin
      for (ProgCntr = 0; ProgCntr < 255; ProgCntr = ProgCntr + 1)
	Prog[ProgCntr] = `NOP;
    $readmemb("Program", Prog);
    ProgCntr = 0;
    $gr_waves(
//	"EntryMatch_v1", top.datapath.EntryMatch_v1,
//	"TagMatch_v1", top.datapath.TagMatch_v1,
//	"ValidMatch_v1", top.datapath.ValidMatch_v1,
//	"TopData_v2", top.CacheData_v2,
//	"PadData_v2", top.CacheDataPad.IntBus_v1,
//	"PadExtData", top.CacheDataPad.ExtBus_v1,
//	"ExtDrvBus", top.CacheDataPad.ExtDrvBus,
//	"ExtData_s2", top.ExtCacheData,
//	"CacheWrite_s2", top.datapath.regfile.CacheWrite_s2,

	// program counter and clocks
	"ProgCntr", ProgCntr,
	"phi1", phi1,
	"phi2", phi2,
	// external signals
	"ExtCacheWrite_s1", ExtCacheWrite_s1,
	"ExtCacheRead_s1", ExtCacheRead_s1,
	"ExtCacheReset_s1", ExtCacheReset_s1,
	// internal signals
	"Tag0", top.datapath.tag.TagReg[0],
	"Data0", top.datapath.regfile.RegFile[0],
	"Tag1", top.datapath.tag.TagReg[1],
	"Data1", top.datapath.regfile.RegFile[1],
	"Tag2", top.datapath.tag.TagReg[2],
	"Data2", top.datapath.regfile.RegFile[2],
	"Tag3", top.datapath.tag.TagReg[3],
	"Data3", top.datapath.regfile.RegFile[3],
	"ValidReg", top.datapath.validbit.ValidReg,
	"Data_v2", top.datapath.CacheData_v2,
	"Addr_v1", top.datapath.CacheAddr_v1,
	"WordLines",top.datapath.WordLines_s1,
	"ValidValue", top.datapath.validbit.ValidValue_v1,
	"Match_v1", top.control.dpcontrol.Match_v1,
	"DP_state", top.control.dpcontrol.present_state_s1,
	"DP_next_state", top.control.dpcontrol.new_state_s2,
	"Bus_state",top.control.buscontrol.state_s1,
	"Bus_next_state",top.control.buscontrol.newstate_s2,
	"WriteTag_s1", top.datapath.WriteTag_s1,
	"HeadTailSel",top.datapath.HeadTailSelect_s1,
	"CacheAddrPadCntl", top.CacheAddrDrv_q1,
	"CacheDataDrvChipCntrl", top.control.CacheDataDrvChip_q2,
	"ChipDataDrvCacheCntrl", top.control.ChipDataDrvCache_q2,
	"CacheWrite_s2", top.control.CacheWrite_s2,
	"CacheRead_s2", top.control.CacheRead_s2,
	// external signals
	"CacheAddr_s1", CacheAddr_s1,
	"CacheData_s2", CacheData_s2,
	"Head",top.datapath.HeadLines_s1,
	"Tail",top.datapath.TailLines_s1,
	"TailShiftEn",top.TailShiftEnable_s2,
	"HeadShiftEn",top.HeadShiftEnable_s2,
	"WriteStall_s2", WriteStall_s2,
	"ReadStall_s2", ReadStall_s2,
	"ReadMatch_s2", ReadMatch_s2,
	"BusGrant_s2", BusGrant_s2,
	"WriteDone_s1", WriteDone_s1,
	"BusRelease_s2", BusRelease_s2,
	"WriteMem_s1", WriteMem_s1,
	"BusRequest_s2", BusRequest_s2,
	"SysBusAddr", SysBusAddr,
	"SysBusData", SysBusData);
    end

  // feed _s1 signals to the chip
  always @(posedge phi2)
    begin
      if (Prog[ProgCntr] == `NOP) $stop;
      else
	begin
	  #5
	  Temp = Prog[ProgCntr];
	  {ExtCacheWrite_s1, ExtCacheRead_s1, ExtCacheReset_s1,
	  WriteDone_s1} = Temp[21:18];
	  CacheAddr_s1 = Temp[17:14];
	  WriteMemReg_s1 = Temp[13];
	  ProgCntr = ProgCntr + 1;
	end
    end

  // check _s1 signals from the chip
  always @(phi1 or ExtCacheWrite_s1 or 
	WriteMem_s1 or WriteMemReg_s1 or 
	SysBusAddr or SysBusAddrReg or 
	SysBusData or SysBusDataReg)
    if (phi1)
      begin
	#10
	if (WriteMem_s1 != WriteMemReg_s1)
	  $display("_s1 error: %h, WriteMem_s1 contains %h, not %h.\n", 
		ProgCntr, WriteMem_s1, WriteMemReg_s1);
	if (WriteMem_s1)
	  begin
	    if (SysBusAddr != SysBusAddrReg)
	      $display(" error: %h, SysBusAddr contains %h, not %h.\n",
		ProgCntr, SysBusAddr, SysBusAddrReg);
	    if (SysBusData != SysBusDataReg)
	      $display(" error: %h, SysBusData contains %h, not %h.\n",
		ProgCntr, SysBusData, SysBusDataReg);
	  end
      end

  // latch ExtCacheWrite_s1
  always @(phi1 or ExtCacheWrite_s1)
    if (phi1)
      ExtCacheWrite_s2 = ExtCacheWrite_s1;

  // load cache data onto bus
  assign CacheData_s2 = ExtCacheWrite_s2 ? CacheDataToChip_s2 : 4'bz;

  // feed _s2 signals to the chip
  always @(posedge phi1)
    begin
      if (Prog[ProgCntr] == `NOP) $stop;
      else
	begin
	  #5
	  Temp = Prog[ProgCntr];
	  BusGrant_s2 = Temp[21];
	  CacheDataToChip_s2 = Temp[20:17];
	  CacheDataFromChip_s2 = Temp[16:13];
	  {WriteStallReg_s2, ReadStallReg_s2, ReadMatchReg_s2, 
		BusReleaseReg_s2, BusRequestReg_s2} = Temp[12:8];
	  SysBusAddrReg = Temp[7:4];
	  SysBusDataReg = Temp[3:0];
	  ProgCntr = ProgCntr + 1;
	end
    end

  // check _s2 signals from the chip
  always @(phi2 or WriteStall_s2 or WriteStallReg_s2 or 
	ReadStall_s2 or ReadStallReg_s2 or
	BusRelease_s2 or BusReleaseReg_s2 or 
	BusRequest_s2 or BusRequestReg_s2 or 
	ReadMatch_s2 or ReadMatchReg_s2 or 
	CacheData_s2 or CacheDataFromChip_s2)
    if (phi2)
      begin
	#10
	if (WriteStall_s2 != WriteStallReg_s2)
	  $display("_s2 error: %h, WriteStall_s2 contains %h, not %h.\n",
		ProgCntr, WriteStall_s2, WriteStallReg_s2);
	if (ReadStall_s2 != ReadStallReg_s2)
	  $display("_s2 error: %h, ReadStall_s2 contains %h, not %h.\n",
		ProgCntr, ReadStall_s2, ReadStallReg_s2);
	if (BusRelease_s2 != BusReleaseReg_s2)
	  $display("_s2 error: %h, BusRelease_s2 contains %h, not %h.\n",
		ProgCntr, BusRelease_s2, BusReleaseReg_s2);
	if (BusRequest_s2 != BusRequestReg_s2)
	  $display("_s2 error: %h, BusRequest_s2 contains %h, not %h.\n",
		ProgCntr, BusRequest_s2, BusRequestReg_s2);
	if (ReadMatch_s2 != ReadMatchReg_s2)
	  $display("_s2 error: %h, ReadMatch_s2 contains %h, not %h.\n",
		ProgCntr, ReadMatch_s2, ReadMatchReg_s2);
	else
	  begin
	    if (ReadMatch_s2)
	      begin
		if (CacheData_s2 != CacheDataFromChip_s2)
		  $display("_v2 error: CacheData contains %h, not %h.\n",
			ProgCntr, CacheData_s2, CacheDataFromChip_s2);
	      end
	  end
      end

endmodule