/////////////////////////////////////////////////////////////////////////////
// Block Name:  top.v
// Author:      Lin Ma & Sopan Joshi
/////////////////////////////////////////////////////////////////////////////
module top();
/////////////////////////////////////////////////////////////////////////////
  wire			phi1,           // clock phase 1
			phi2,           // clock phase 2
  			ExtCacheWrite_s1,
			ExtCacheRead_s1,
			ExtCacheReset_s1,
			WriteStall_s2, 
			ReadStall_s2, 
			ReadMatch_s2,
			BusGrant_s2, 
			WriteDone_s1,
			BusRelease_s2, 
			WriteMem_s1, 
			BusRequest_s2,
			Match_v1, 
			ValidValue_v1,
			WriteTag_s1, 
			WriteValid_s1,
			CacheWrite_s2, 
			CacheRead_s2,
			SysBusRead_s1, 
			SysBusRead_s2,
			CacheAddrDrv_q1,
			CacheDataDrvChip_q2,
			ChipDataDrvCache_q2,
			HeadShiftEnable_s2, 
			TailShiftEnable_s2, 
			HeadTailReset_s2, 
			HeadTailSelect_s1;

  wire		[3:0]	ExtCacheAddr_s1,
			ExtCacheData_s2,
			SysBusData_s1,
			SysBusAddr_s2,
			CacheAddr_v1,
			CacheData_v2,
			ExtSysBusAddr_s1,
			ExtSysBusData_s1;

`define ZERO		1'b0

  // Instantiate portions of chip
  control	control(phi1, phi2, 
			ExtCacheWrite_s1, ExtCacheRead_s1, ExtCacheReset_s1,
			WriteStall_s2, ReadStall_s2, ReadMatch_s2,
			BusGrant_s2, WriteDone_s1,
			BusRelease_s2, WriteMem_s1, BusRequest_s2,
			Match_v1, ValidValue_v1,
			WriteTag_s1, WriteValid_s1,
			CacheWrite_s2, CacheRead_s2,
			SysBusRead_s1, SysBusRead_s2,
			HeadShiftEnable_s2, TailShiftEnable_s2, 
			HeadTailReset_s2, HeadTailSelect_s1,
			CacheAddrDrv_q1, 
			// right here!
			CacheDataDrvChip_q2, ChipDataDrvCache_q2);

  datapath	datapath(phi1, phi2, 
			CacheAddr_v1, ExtCacheAddr_s1, CacheData_v2,
			WriteTag_s1, WriteValid_s1, ValidValue_v1, 
			ExtCacheReset_s1, CacheWrite_s2, CacheRead_s2, 
			SysBusRead_s1, SysBusRead_s2,
			HeadShiftEnable_s2, TailShiftEnable_s2, 
			Match_v1, SysBusData_s1, SysBusAddr_s2, 
			HeadTailReset_s2,HeadTailSelect_s1);

  pad		SysBusAddrPad(`ZERO, WriteMem_s1, 
			ExtSysBusAddr_s1, SysBusAddr_s2);

  pad		SysBusDataPad(`ZERO, WriteMem_s1, 
			ExtSysBusData_s1, SysBusData_s1);

  pad		CacheAddrPad(CacheAddrDrv_q1, `ZERO, 
			ExtCacheAddr_s1, CacheAddr_v1);

  pad		CacheDataPad(CacheDataDrvChip_q2, ChipDataDrvCache_q2,
			ExtCacheData_s2, CacheData_v2);

  // Instantiate testing infrastructure
  clkgen	clkgen(phi1, phi2);

  stimulus	stimulus(phi1, phi2,
		// signals from cache to chip
		ExtCacheWrite_s1, ExtCacheRead_s1, ExtCacheReset_s1,
		ExtCacheAddr_s1, ExtCacheData_s2,
		// signals from chip to cache
		WriteStall_s2, ReadStall_s2, ReadMatch_s2,
		// signals from bus to chip
		BusGrant_s2, WriteDone_s1,
		// signals to bus from chip
		BusRelease_s2, WriteMem_s1, BusRequest_s2,
		SysBusAddr_s2, SysBusData_s1);

	snooper	snooper(
	phi1, phi2, ExtCacheWrite_s1, ExtCacheRead_s1, 
	ExtCacheReset_s1, WriteStall_s2, ReadStall_s2, ReadMatch_s2, 
	BusGrant_s2, WriteDone_s1, BusRelease_s2, WriteMem_s1, 
	BusRequest_s2, ExtCacheAddr_s1, ChipDataDrvCache_q2, ExtCacheData_s2, 
	ExtSysBusAddr_s1, ExtSysBusData_s1);

endmodule